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Si5040
10 Gbps XFP T RANSCEIVER W I T H J I T T E R A TTENUATOR
Features
Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring
independent CDRs, DSPLL ? -based jitter-attenuating CMUs, and data retimers in both
transmit and receive directions.
Si5100
?
?
DSPLL-based, jitter-attenuating CMUs ?
in both transmit and receive directions
Frequency-agile jitter filtering from 9.8 to ?
11.35 Gbps (continuous)
Transmitter jitter generation 2.5 mUI rms
(typical)
Automatic slicing level adjustment with
optional programmable override
?
Compliant to XFP specifications and
jitter specifications for telecom
(SONET/SDH, OTU-2) and datacom
(10 GbE/10 GbE+FEC and
10 GFC/10 GFC+FEC) applications
?
?
Programmable sample phase
adjustment
Line loopback, XFI loopback, pattern
generation, and pattern check test
capabilities
Ordering Information:
?
?
?
Supports referenceless operation
Integrated limiting amplifier provides
better than 8 mV receiver sensitivity
User-programmable receiver loss-of-
?
?
?
?
1.8/3.3 V or single 1.8 V supply
575 mW (typ) power dissipation
5x5 mm LGA package
Serial microcontroller interface control
See page 103.
signal (LOS) detector
Applications
Pin Assignments
Si5040
(Transparent Top View)
?
?
?
XFP telecom modules
XFP datacom modules
Optical test equipment
?
Jitter-attenuation and signal
regeneration of 10 Gbps serial signal
on line cards
Description
The Si5040 is a complete, low-power, high-performance XFP transceiver suitable for
GND
RX_LOL
RX_LOS
VDDIO
1
2
3
4
32
31
30
GND
PAD
29
28
27
GND
PAD
26
25
24
23
22
21
SCK
GND
TD+
TD–
multiple XFP module types, from short-reach datacom to long-reach telecom
GND
5
20
GND
applications. The Si5040 integrates a rate-agile, programmable-bandwidth, jitter-
attenuating CMU in the transmit direction, which significantly attenuates jitter present at
RXDIN–
RXDIN+
6
7
GND
PAD
GND
PAD
19
18
RD+
RD–
the XFI interface and on the applied reference clock, removing the need for an external
jitter cleanup circuit. The device supports referenceless operation or operation with a
GND
8
9
10
11
12
13
14
15
16
17
GND
synchronous or asynchronous reference clock. The device can be completely configured
through a serial microcontroller interface. The Si5040 is compliant with all XFP
requirements in both datacom and telecom applications. The Si5040 is packaged in a
5x5 mm LGA package and dissipates 575 mW (typ).
Functional Block Diagram
Program
RX_LOS
RX_LOL
RXDIN
mable
Equalizer
LA
CDR
Clk
D
FIFO
CML
RD
Interrupt
Control
XFI
DSPLL TM
Jitter Attenuator
Loopback
Line
Loopback
RefCLK
(optional)
Serial
Interface
Serial
Port
DSPLL TM
Jitter Attenuator
Clk
TXDOUT
CML
FIFO
D
CDR
Equalizer
TD
Rev. 1.3 6/12
Copyright ? 2012 by Silicon Laboratories
Si5040
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